Reliability: the next frontier
نویسنده
چکیده
The goal of my graduate research has been finding architectural solutions to key technological challenges facing processor design that impact reliability, power, and performance of multicores. The rapidly shrinking feature sizes provided by the Moore’s Law with each successive technology generation make the devices on a chip increasingly susceptible to soft errors, hard errors, process variation, and wearout or aging. The emphasis of my research is to build reliable systems with unreliable components. Up until now, reliability was the domain of a relatively small group of researchers. Now it has become the concern of the whole community of computer architects. Reliability is emerging as a first order design constraint, which will directly impact a processor’s performance. Two key reliability challenges due to technology scaling that directly impact performance are process variation and aging or wearout. Process variation causes a spatial variation of transistor properties across a chip, whereas aging causes a temporal variation. To account for this variation in transistor speeds, the designer must provide conservative guardbands by clocking the chip at lower than nominal frequencies, resulting in unnecessary performance losses. In addition to technology issues, reliability problems are also introduced due to hardware design bugs. Such bugs could have significant cost implications for processor design. Perhaps the most notorious is the Pentium floating-point division bug that led to a $500 million chip recall. I have investigated process variation, aging, and design defects as described below.
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